Mechatronics Engineering Department
  • Home
  • About
  • People
  • Academics
    • Undergraduate >
      • CHEP >
        • Program
        • Schedules
        • Contact Forms >
          • Course_Reg
        • Curriculum
      • Mainstream Program >
        • Class Schedules >
          • Third year Mechatronics
          • Fourth year Mechtronics
        • Courses >
          • Third year Mechatronics
          • Fourth year Mechatronics
        • Curriculum Plan
        • Graduation Projects
    • Postgraduate >
      • Class Schedules
      • Spring 2014 Exam Schedule
      • Courses
      • Arabic Curriculum Plan
      • English Curriculum Plan
      • Awarded Theses
      • Study Manual
      • Administrative Processes >
        • M.Sc. Admission Process
        • M.Sc. Registeration Process
        • M.Sc. Thesis Defense Process
        • PhD Admission Process
        • PhD Thesis Defense Process
  • Research
    • Current Research Tracks
    • Previous Research Projects
  • Resources
    • Forms
    • FAQ
    • Laboratories >
      • Mechatronics Lab.
      • Automatic Control Lab.
      • Motion Control lab.
      • Pneumatic and Hydraulic Lab
    • Photo Library >
      • Mechatronics Lab and Staff Photos
      • Motion Control Lab Photos
      • Pneumatic and Hydraulic Lab Photos
    • Video Library >
      • ASU Mechatronics department on TV
      • Lab sessions
      • Graduation Projects
    • Mechatronics Calendar
    • Lab Reservation
    • Useful Links
  • Contact us
  • MCT382

CSE115: Digital Design


Course Home   


Syllabus             


Lecture Notes    <


Assignments     


Feedback                 




Lec #
1
2
3
4
5
6

7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25


Title
Introduction
Number Systems
Binary System Operations
Coding
Boolean Switching Algebra
Combinational Circuit Analysis
Combinational Circuit Synthesis
Karnaugh Maps
Prime Implicants
Four Variable Karnaugh Maps
Simplifying Product of Sums
Don't Care Conditions
Combinational Logic Design Practices
Programmable Logic Arrays
Decoders
Encoders
Three State Logic
Multiplexers & Demultiplexers
XORs and Parity Circuits
Comparators, Adders and Subtractors
Combinational Multipliers and ROMs
VHDL
Latches & Flip-Flops`
State Machines
Timing, Counters, and Shift Registers
Link
Download
Download
Download
Download
Download
Download
Download
Download
Download
Download
Download
Download
Download
Download
Download
Download
Download
Download
Download
Download
Download
Download
Download
Download
Download


Copyright 2014 - Mechatronics Department - Ain Shams University